1. Field of the Invention
The present invention relates to a semiconductor-device manufacturing method and an exposure method.
2. Description of the Related Art
As one of conventional techniques for forming a line-and-space pattern with a pitch finer than a resolution limit in an exposure technique, a technique for a sidewall fabrication process has been developed (for example, see Japanese Patent Application Laid-open No. 2002-280388). However, in the line-and-space pattern formed by the sidewall fabrication process, displacement of line portions may occur due to a shape error of core members used to form a sidewall layer. When a pattern B is formed by being overlaid with an underlying pattern A formed by sidewall fabrication, in conventional techniques, even if displacement due to the sidewall fabrication process occurs in the underlying pattern A, the flow advances to a subsequent process if an overlay error of the underlying pattern A and the pattern B meets a predetermined overlay specification. If the displacement in the underlying pattern A is not considered, there is a high possibility of causing yield degradation. Furthermore, if the overlay specification for the overlay error of the underlying pattern A and the pattern B is uniformly tightened by adding an amount of possible displacement in the underlying pattern A due to the sidewall fabrication, an exposure device having a high overlay accuracy is required, which results in an increase in cost. Moreover, tightening of the overlay specification leads to a drop in reworking rate. Consequently, a reduction of productivity has become a problem.